CLKDIV=CMP_PCLK, INV=INPUT_NOT_INVERTED, MODE=INACTIVE_NO_PULL_DO, HYS=DISABLE, OD=DISABLE, S_MODE=BYPASS_INPUT_FILTER
Digital I/O control for port 2 pins PIO2_0 to PIO2_13. Without glitch filter.
| RESERVED | Reserved. Only write 0 to these bits. |
| MODE | Selects function mode (on-chip pull-up/pull-down resistor control). 0 (INACTIVE_NO_PULL_DO): Inactive (no pull-down/pull-up resistor enabled). 1 (PULL_DOWN_RESISTOR_E): Pull-down resistor enabled. 2 (PULL_UP_RESISTOR_ENA): Pull-up resistor enabled. 3 (REPEATER_MODE): Repeater mode. |
| HYS | Hysteresis. 0 (DISABLE): Disable. 1 (ENABLE): Enable. |
| INV | Invert input 0 (INPUT_NOT_INVERTED): Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 (INPUT_INVERTED_HIGH): Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). |
| RESERVED | Reserved. |
| OD | Open-drain mode. 0 (DISABLE): Disable. 1 (OPEN_DRAIN_MODE_ENAB): Open-drain mode enabled. This is not a true open-drain mode. |
| S_MODE | Digital filter sample mode. 0 (BYPASS_INPUT_FILTER): Bypass input filter. 1 (1_CLOCK_CYCLE): 1 clock cycle. Input pulses shorter than one filter clock are rejected. 2 (2_CLOCK_CYCLES): 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 3 (3_CLOCK_CYCLES): 3 clock cycles. Input pulses shorter than three filter clocks are rejected. |
| CLKDIV | Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. 0 (CMP_PCLK): CMP_PCLK. 1 (CMP_PCLKDIV2): CMP_PCLK/2. 2 (CMP_PCLKDIV4): CMP_PCLK/4. 3 (CMP_PCLKDIV8): CMP_PCLK/8. 4 (CMP_PCLKDIV16): CMP_PCLK/16. 5 (CMP_PCLKDIV32): CMP_PCLK/32. 6 (CMP_PCLKDIV64): CMP_PCLK/64. |
| RESERVED | Reserved. |